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Intel's Raja Koduri teases Xe-powered graphics chips

Intel's new Xe chips appear to use a tiled design, bringing multi-chip to the GPU market

Intel's Raja Koduri teases Xe-powered graphics chips

Intel's Raja Koduri teases Xe-powered graphics chips

Intel's Xe graphics architecture is designed to scale from integrated graphics to ultra-high-end data centre environments. We already know that Intel's Xe graphics are coming to Intel's upcoming Tiger Lake series of mobile processors, but after that will come something much bigger. 

Raja Koduri, Intel's chief architect, has released images of Intel Xe accelerator chips, showcasing what appears to be a tiled design which scales from single-chip (top right) to dual-chip (left) and four-chip (bottom left) models. The latter of these designs are referred to as BFP (big 'fabulous' package), by Raja in a recent Tweet

Intel believes that a multi-chip design approach will give them a considerable advantage within the data centre market; providing them with similar benefits to AMD's multi-chip design approach to its EPYC series of server processors. That said, these benefits may not be shared with the PC graphics market, as gaming workloads are latency-sensitive, and the most substantial disadvantage of multi-chip designs are added latencies.  

Right now, Intel's Xe-HP accelerators are currently being tested within Intel's Folsom labs, and at this time it is unknown when the company plans to release their first Xe-powered datacenter accelerators. 

Intel's Raja Koduri teases Xe-powered graphics chips  

You can join the discussion on Intel's Xe-HP accelerator teaser on the OC3D Forums

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Most Recent Comments

25-06-2020, 05:47:05

Warchild
Interseting to see an IHS used in a GPU. Unless this is purely to focus on discretion and secrecy for the time being.Quote

25-06-2020, 06:01:38

WYP
Quote:
Originally Posted by Warchild View Post
Interseting to see an IHS used in a GPU. Unless this is purely to focus on discretion and secrecy for the time being.
With the designs being early it is likely that they are mounted and unmounted frequently from testing setups. An IHS will prevent die cracking. These accelerator chips are socketed.Quote

25-06-2020, 07:09:06

tgrech
Very cool they've found a market to commercialise and develop MCM GPU technology, if these interconnects are at least becoming viable in terms of bandwidth then I guess CDNA and NVidia's post-Ampere compute orientated dies are probably on a pretty similar development path, given both companies have also got a wealth of research or commercial designs in the area. (Unless either company has already committed to only using MCM's when its viable across their ranges, AMD may want to do that in particular to avoid an expensive switchover period if they're not sure they'll get the design wins)Quote

25-06-2020, 12:16:54

NeverBackDown
Wonder how much extra performance that AA battery gives on the left Quote

25-06-2020, 12:47:39

AlienALX
One of them makes threadripper look positively small Quote
Reply
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