TSMC reveals Wafer-on-Wafer chip stacking technology - WoW!

Vertically stacked silicon for future HPC products

TSMC starts 7nm volume production

TSMC reveals Wafer-on-Wafer chip stacking technology

At the TSMC Technology Symposium, the company has unveiled their new Wafer-on-Wafer (WOW) technology, a form of 3D stacking for silicon wafers. The new technique can connect chips on two silicon wafers using through-silicon via (TSV) connections, acting similarly to today's 3D NAND technology. 

This technique is different to what we see today with some multi-die silicon, which has multiple dies sit side-by-side wither on top of an interposer or using Intel's EMIB technology. TSMC's WoW technology can connect two dies directly and with minimal data transfer times thanks to the small distance between chips, creating silicon which offers high levels of performance and a smaller overall footprint. 

Notice that this new tech is called Wafer-on-Wafer and not die-on-die, this technique stacks silicon while it is still within its original wafer, offering advantages and disadvantages.  

The advantage here is that this tech can connect two wafers of dies at once. Imagine an alternative method where we connect individual dies in the same way, offering a lot less parallelisation within the manufacturing process and the possibility of higher end costs. 

With Wafer-on-Wafer technology, the problem comes when faulty dies on each layer merge to working chips on the second layer, lowering overall yields. This issue prevents this technology from being viable for silicon that doesn't already offer high-yields on a wafer-by-wafer basis. Ideally, chip yields should be 90% or higher to use TSMC's Wafer-on-Wafer technology. 

Another potential issue comes when two heat producing pieces of silicon are stacked on top of each other, creating a situation where heat density could become a limiting factor for stacked silicon. This thermal concern makes WoW connected chips most suitable for low-power silicon, where heat is less of an issue. 

TSMC reveals WoW chip stacking technology

TSMC currently manufactures graphics cards for both AMD and Nvidia as well as the silicon used for all major games consoles, giving this technology the potential to improve a wide range of future products. The one remaining question is this process' viability when used with high-powered components. 

The direct die-to-die connectivity of WoW technology allows silicon to communicate exceptionally quickly and with minimal latencies, opening up the possibility of chip creation where two dies can be interconnected with few downsides.

You can join the discussion on TSMC's new Wafer-on-Wafer chip stacking technology on the OC3D Forums

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Most Recent Comments

02-05-2018, 15:30:31

Now that's progress!Quote

02-05-2018, 16:13:34

Pretty cool. I would imagine this would help a lot for mobile however considering they have to produce so many it probably will be a while before they are able to get good enough yields.Quote

02-05-2018, 16:41:48

LOL, the lower wafer in the stack will burn like a star having to conduct it's heat trough all the other layers before it reaches the heatsink.Quote

02-05-2018, 18:23:22

Originally Posted by meuvoy View Post
LOL, the lower wafer in the stack will burn like a star having to conduct it's heat trough all the other layers before it reaches the heatsink.
The idea is the low power stuff is on the bottom, like cache and dedicated encoder/decoder and perhaps memory controller, while the top layer is just connected cores.

That's from the patent filings TSMC published.Quote

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