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TSMC Paves the way to 5nm with Full Design Tools - Promises Performance and Density Boosts

5nm is set to offer a huge step up in logic scaling over 7nm

TSMC Paves the way to 5nm with Full Design Tools - Promises Performance and Density Boosts

TSMC Paves the way to 5nm with Full Design Tools - Promises Performance and Density Boosts

Later this year we can expect a massive influx of 7nm silicon to enter the consumer market, but on the horizon, we can already see the market prepare for the next big node transition. 

Yes, 7nm is a significant node shift for the industry, seeing product designs which range from high power/performance computing devices and smaller, low-power mobile devices alike, but that doesn't mean that manufacturers like TSMC and Samsung can sit on their laurels. In the coming years, we will see two innovations grip the lithography landscape, with EUV nodes and advanced 5nm nodes being on the horizon. 

TSMC has announced that they have completed the infrastructure design of their upcoming 5nm process node, their second generation EUV process node which promises improved performance and silicon density over 7nm. Now TSMC has been able to certify full-line EDA (Electronic Design Automation) tools that will allow companies to design products that will be based on the upcoming node.  

When building an ARM Cortex-A72 core, TSMC has found that 5nm can offer a 1.8x increase in logic density over 7nm and deliver a 15% speed gain. On top of this TSMC boasts "superior SRAM and analog area reduction", all of which will be big selling points for the node. TSMC's 5nm process node is already in risk production.   

TSMC Paves the way to 5nm with Full Design Tools - Promises Performance and Density Boosts  

Much like 7nm, TSMC is targetting 5nm at both low-power mobile products and high-performance computing applications, allowing the node to scale well from desktop-grade processors and graphics cards to mobile phones, tablets and a range of other connected devices. 

TSMC's 5nm process is expected to enter Volume production in late 2020. 

You can join the discussion on TSMC's 5nm performance claims and design tools on the OC3D Forums

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Most Recent Comments

08-04-2019, 12:04:20

NeverBackDown
Very impressiveQuote

09-04-2019, 03:22:45

Warchild
Setting themselves for world domination if they can pull this off.Quote

09-04-2019, 03:43:07

Dicehunter
Pretty cool, I'm very curious as to when silicon will no longer be viable as a material due to physical constraints.Quote

09-04-2019, 03:56:01

Warchild
Quote:
Originally Posted by Dicehunter View Post
Pretty cool, I'm very curious as to when silicon will no longer be viable as a material due to physical constraints.
There is already a better alternative by using Black Phosphorus. The drawback is that they still do not have an optimum method of mass producing a wafer. If successful though you would expect far lower voltages due to the higher carrier mobility. Basically electrons flow faster and easier through BP than silicon. That would mean far better power consumption.

Drawback though was that making thin layers used a scraping technique from crystal BP. So its far from ideal.Quote
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