Samsung's new process roadmap now extends down to 4nm

Samsung's new process roadmap now extends down to 4nm

Samsung's new process roadmap now extends down to 4nm

Samsung's new process roadmap now extends down to 4nm

 
As time moves on technology has continued to get smaller and smaller, allowing PCs which once filled entire rooms to be condensed into something that can now fit into the palm of your hand. 
 
When creating CPUs, GPUs and all other silicon products process technology has always been at the forefront of innovation. Every node improvement has over time allowed companies to create products that run faster, consume less power and come in increasingly smaller form factors. Today things have slowed down, with it becoming increasingly difficult to create smaller transistors or to improve their power or performance characteristics, making every advantage count in today's Foundry market.    
 
Samsung has now revealed a detailed roadmap of their future foundry plans, which will continue to create more advanced manufacturing processes and even move beyond modern Silicon FinFET transistors to create what is called a Gate All Around FET (GAAFET) transistor, which promises to overcome the limitation of FinFETs.
 
These plans will lead to 8nm, which will come after Samsung's new 10nm manufacturing process, with Samsung planning on adopting EUV (Extreme Ultra Violet) technology before moving down to 7nm and beyond. The adoption of EUV technology has been very slow, despite the promise of the tech being the saviour that would facilitate the creation of ever denser manufacturing processes.  
 
The adoption of EUV technology has been very slow, despite the promise of the tech being the saviour that would facilitate the creation of ever denser manufacturing processes. This has been due to the sheer complexity of this new technology, which makes sense given the levels of density that manufacturers want to achieve. A silicon Atom is a mere 0.2nm in size, which then needs to to be arranged into a complex, usable circuit to create a modern processor, a crazy feat that is getting increasingly difficult to improve.
 
Right now Samsung's EUV testing has been able to yeild 1,000 silicon wafers per day, with a goal of 1,500 wafers per day making the company a sustainable investment/return ratio. Right now Samsung are confident that they can achieve 1,500 wafer per day, if nore more.  

  

Samsung's new process roadmap now extends down to 4nm  

Samsung’s newest foundry process technologies and solutions introduced at the annual Samsung Foundry Forum include:

  • 8LPP (8nm Low Power Plus): 8LPP provides the most competitive scaling benefit before transitioning to EUV (Extreme Ultra Violet) lithography. Combining key process innovations from Samsung’s 10nm technology, 8LPP offers additional benefits in the areas of performance and gate density as compared to 10LPP.

 

  • 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore’s law scaling, paving the way for single nanometer semiconductor technology generations.

 

  • 6LPP (6nm Low Power Plus): 6LPP will adopt Samsung’s unique Smart Scaling solutions, which will be incorporated on top of the EUV-based 7LPP technology, allowing for greater area scaling and ultra-low power benefits.

 

  • 5LPP (5nm Low Power Plus): 5LPP extends the physical scaling limit of FinFET structure by implementing technology innovations from the next process generation, 4LPP, for better scaling and power reduction.

 

  • 4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation device architecture – MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung’s unique GAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture.

 

  • FD-SOI (Fully Depleted – Silicon on Insulator): Well suited for IoT applications, Samsung will gradually expand its 28FDS technology into a broader platform offering by incorporating RF (Radio Frequency) and eMRAM(embedded Magnetic Random Access Memory) options. 18FDS is the next generation node on Samsung’s FD-SOI roadmap with enhanced PPA (Power/Performance/Area).

 

What needs to be remembered here is that modern process names are meaningless for most modern foundries, acting as marketing terms rather than physical characteristics of each manufacturing process, so 4nm will likely not be a true 4nm. 

Looking at other companies we can see that TSMC's planned 7nm manufacturing node has a larger gate size than Intel's 10nm process, which doesn't make any sense. Looking again at TSMC we know that their new 12nm manufacturing process is an improved version of their 16nm process, with 12nm truly being a 16nm+ node, rather than something smaller. 

 

You can join the discussion on Samsung's Foundry Plans on the OC3D Forums

 

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Most Recent Comments

25-05-2017, 13:05:17

NeverBackDown
Gotta love the marketing ploys here.

There 4nm stuff probably won't be for high performance designs. Probably at most for mobileQuote

26-05-2017, 03:49:57

SeekaX
Isn't that well into the realm of quantum mechanics stuff we can't handle? Would be interesting to know how they are getting there.Quote
Reply
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