PCI-SIG announces PCIe 6.0, because who doesn't want more bandwidth?

Expect a PCIe 5.0 replacement in 2021

PCI-SIG announced PCIe 6.0, because who doesn't want more bandwidth?

PCI-SIG announces PCIe 6.0, because who doesn't want more bandwidth?

PCIe 4.0 is in its infancy, and PCIe 5.0 has recently been ratified (more info here), but that doesn't mean that the march of progress should stop there. PCI-SIG wishes to remain the king of PC interconnects, and that means that they need to continue to evolve while maintaining backwards compatibility. 

Now, PCIe 6.0 is the new hotness, packing a 2x increase in transfer speeds over PCIe 5.0, a 4x boost in raw bit rate over PCIe 4.0 and a whopping 8x improvement over the 32GB/s of bandwidth that an x16 PCIe 3.0 configuration can offer. 

PCIe 6.0 is a standard that's currently within its planning stages, with PCI-SIG planning to ratify and release their full standard in 2021, two years after the release of PCIe 5.0. In the PC space, it typically takes two years for PCIe standards to make it into the PC market, making it probable that we will start seeing PCIe 6.0 compliant PCs in 2023 or 2024. 

Below is a brief overview of the PCIe 6.0 standard, in its current form.

PCIe 6.0 Specification Features

- Delivers 64 GT/s raw bit rate and up to 256 GB/s via x16 configuration
- Utilises PAM-4 (Pulse Amplitude Modulation with four levels) encoding and leverages existing 56G PAM-4 in the industry
- Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
- Maintains backwards compatibility with all previous generations of PCIe technology

PCI-SIG announced PCIe 6.0, because who doesn't want more bandwidth?  

To put the performance of PCIe 6.0 into context, it could enable M.2 devices to deliver speeds that are up to eight times faster than today's Samsung 970 Pro series SSD, which is widely regarded as one of the best performing M.2 SSDs on the market. Another way to put it is with PCIe 6.0, the performance of a PCIe 3.0 16x configuration is equivalent to two PCIe 6.0 lanes. 

PCIe 6.0 will enable higher levels of bandwidth for those who need it while granting PC users access to today's bandwidth levels over fewer PCIe lanes. The only problem with this rapid evolution is that new PCIe 4.0 devices will soon find themselves replaced with PCIe 5.0 and then PCIe 6.0 over the next 5 or so years. That said, should e complain about things progressing too quickly? 

You can join the discussion on PCI-SIG's upcoming PCIe 6.0 standard on the OC3D Forums

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Most Recent Comments

19-06-2019, 09:10:52

I always wonder how they come up with their definitions. Is there a team of researchers around there that tells them what should be doable at that time or how does the definition work? It feels like somebody just yells "FASTER!" every now and then and then his peasants say "okay" and just *insert multiplier here* the rates

Can someone please enlighten me Quote

19-06-2019, 13:28:34

PCI-SIG is a non-profit consortium mostly made up of engineers from a variety of other companies, they work out the spec over a long series of meetings, generally different companies end up having differing levels of influence & investment on each spec, but hardware vendors need to be imminently involved as at least one of them needs to create test silicon to validate the 0.7 spec. Definitely the most time consuming part with PCIe4 was just working out & agreeing on what was possible, which mostly comes from analysis & validation of new techniques for safely increasing signal rate or encoding efficiency. While a combination of two techniques was eventually found that could hit the goal of 16GT/s, there was disagreement on whether the initial plans for PCIe4 would actually be able to achieve those speeds practically in most devices & workloads and so quite a few further refinements had to be made to the 0.7 spec. These are the steps taken in development of a new PCIe spec:

Draft 0.3 (Concept): this release may have few details, but outlines the general approach and goals. For PCIe 4.0 this included the 16 GT/s signaling rate, re-use of the 128/130 encoding scheme developed for PCI 3.0 8 GT/s mode, maintaining full backwards compatibility, etc. and was released in February 2014.
Draft 0.5 (First draft): this release has a complete set of architectural requirements and must fully address the goals set out in the 0.3 draft. The PCIe 4.0 Draft 0.5 specification was released in February 2015.
Draft 0.7 (Complete draft): this release must have a complete set of functional requirements and methods defined, and no new functionality may be added to the specification after this release. Before the release of this draft, electrical specifications must have been validated via test silicon. For PCIe 4.0, two independent implementations were provided to PCI-SIG workgroup members, one from Synopsys, and the other from Mellanox. The PCIe 4.0 Draft 0.7 was released November 15, 2016.
Draft 0.9 (Final draft): this release allows PCI-SIG member companies to perform an internal review for intellectual property, and no functional changes are permitted after this draft.
1.0 (Final release): this is the final and definitive specification, and any changes or enhancements will be through Errata documentation and Engineering Change Notices (ECNs) respectively.
Full article from a Synposys engineer who was heavily involved with PCIe4's practical development: https://www.chipestimate.com/PCI-Exp...cle/2017/02/21Quote

23-06-2019, 18:03:54

The best part about this is they say compared to 5.0 specification the length should remain almost exactly the same. So you're doubling the speed without making the length shorter. That's impressive. That should also really help lower cost for consumers and Enterprise boards.Quote

24-06-2019, 09:09:45

Showing more bandwidth into lanes proved expensive for PCI-E 4. How viable will it be for manufacturers to maintain signal integrity for faster standards over long lanes is to bee seen. It can be done. But at what price?

ASUS showcased Prime Utopia concept. Going away from ATX standard. Maybe in the future will be more profitable, or necessary to change the standard to accommodate uber fast lanes.Quote

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