Samsung ships 1 million 10nm-class EUV memory chips – Details DDR5 Production Timeline

Samsung ships 1 million 10nm-class EUV memory chips - Details DDR5 Production Timeline

Samsung ships 1 million 10nm-class EUV memory chips – Details DDR5 Production Timeline

Samsung has announced that they have managed to ship over 1 million 10nm-class DDR4 memory modules that are based on the company’s Extreme Ultraviolet (EUV) technology, opening the door to increased use of cutting-edge EUV lithography within the PC market. 

EUV lithography will form the basis of Samsung’s future memory technologies, reducing the need for multi-pattering techniques while delivering increased accuracy during the manufacturing process. This allows Samsung to increase the performance of its memory offerings while also increasing their manufacturing yields and shortening the company’s development time. 

In all, Samsung’s use of EUV lithography technology has been a huge win for the company’s memory manufacturing business, and the company expects EUV to reach full deployment with its future DRAM generations. This will start with the company’s new 10nm-class D1a DRAM.   

In 2021, Samsung expects to start mass-producing DDR5/LPDDR5 DRAM using its D1a technology. This will line up well with the PC industry’s move to DDR5-based memory, and the increasing use of LPDDR5 DRAM within the mobile market. 

Samsung ships 1 million 10nm-class EUV memory chips - Details DDR5 Production Timeline 
In late 2021, AMD is expected to release its Genoa series of EPYC processors and other Zen 4 series processors.  Zen 4 is expected to make a move to DDR5 DRAM, a shift which will finally move AMD away from its popular AM4 socket. When this shift happens, DRAM makers will need to be prepared with its DDR5 memory offerings.  

Below is Samsung’s latest DDR memory production timeline. 

Samsung ships 1 million 10nm-class EUV memory chips - Details DDR5 Production Timeline  

You can join the discussion on Samsung’s shift to EUV DRAM manufacturing and their DDR5/LPDDR5 memory plans on the OC3D Forums.Â