'

Samsung reveals 12-layer 3D-TSV chip breakthrough - Huge implications for HBM memory

Ready for 24GB HBM2 packages?

Samsung Introduces HBM2E Memory, Packing a 33% Bandwidth Boost

Samsung reveals 12-layer 3D-TSV chip breakthrough - Huge implications for HBM memory

Samsung Electronics has announced that they have successfully developed the industry's first 12-layer 3D-TSV (Through Silicon Via) technology, creating packages that are the same thickness as today's 8-layer HBM2 (High Bandwidth Memory-2) chips.

Using 60,000 TSV holes, Samsung can vertically stack 12 DRAM chips to create a three-dimensional structure, allowing the company to develop HBM memory chips that are up to 24GB in capacity. This feat is accomplished by stacking 12 16Gb chips. Amazingly, Samsung has been able to achieve this without any increase in size over today's 8GB HBM2 memory packages. 

Thanks to the shorter data transmission time between chips, Samsung's 12-layer 3D-TSV technology can also enable faster memory speeds and lower levels of power consumption than existing wire bonding technologies. 

With this new technology, Samsung's HBM2 memory could be used to create a Radeon VII-style graphics card with up to 96GB of HBM2 memory. Today, HBM2 memory is popular in a variety of use cases that extend from graphics cards to FPGAs and AI accelerators. Offering high capacity HBM memory modules will enable these products to work with larger data sets, which will in-turn help to push these technologies forward. 

At this time, Samsung has not revealed a release timeframe for its 12-layer HBM products, though we expect to hear more in the coming quarters.  
 

Samsung reveals 12-layer 3D-TSV chip breakthrough - Huge implications for HBM memory  
Samsung reveals 12-layer 3D-TSV chip breakthrough - Huge implications for HBM memory  
You can join the discussion on Samsung's 12-layer 3D-TSV technology on the OC3D Forums.  

«Prev 1 Next»

Most Recent Comments

07-10-2019, 12:50:50

NeverBackDown
If it can reduce costs it'll be a winner. Until then for consumer GPUs at least gddr6 makes more sense.Quote

07-10-2019, 12:56:18

WYP
Quote:
Originally Posted by NeverBackDown View Post
If it can reduce costs it'll be a winner. Until then for consumer GPUs at least gddr6 makes more sense.
TBH, this is mostly for FPGA and datacenter/AI-focused GPUs and discrete AI products. Consumer GPUs don't need the capacity (outside of very niche use cases).Quote

07-10-2019, 14:31:10

AngryGoldfish
Very impressive compared to what HBM started out as.Quote

07-10-2019, 21:17:23

Kleptobot
correct me if i'm wrong, but is this an effective bus width increase too? Seeing as you can address more memory addresses off of fewer pins...Quote

08-10-2019, 00:40:55

NeverBackDown
I would assume since they are now using a 3D layout instead of wire tracing, that each TSV would allow more effective data transmission which would result in an overall higher bandwidth. That's also because they have more physical capacity to. So more memory and more efficient data transmission would result in higher overall bandwidth. In a similar form factorQuote
Reply
x

Register for the OC3D Newsletter

Subscribing to the OC3D newsletter will keep you up-to-date on the latest technology reviews, competitions and goings-on at Overclock3D. We won't share your email address with ANYONE, and we will only email you with updates on site news, reviews, and competitions and you can unsubscribe easily at any time.

Simply enter your name and email address into the box below and be sure to click on the links in the confirmation emails that will arrive in your e-mail shortly after to complete the registration.

If you run into any problems, just drop us a message on the forums.