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PCI-SIG's PCI Express 5.0 Standard Is Set to Launch This Quarter

Forget PCIe 4.0, PCIe 5.0 is coming!

PCI-SIG Releases Version 0.9 of their PCI Express 5.0 Standard

PCI-SIG's PCI Express 5.0 Standard Is Set to Launch This Quarter

At CES 2019 PCI Express version 4.0 started to make waves, with AMD confirming that their Zen 2 based Ryzen 3rd Generation and EPYC 2nd Generation processors will offer support for the standard later this year. 

PCIe 4.0 may be in its infancy, but that doesn't mean that PCI-SIG should be standing still. Back in 2017, the organisation announced that they planned to accelerate the development of PCIe 5.0, with plans to deliver a 4x increase in per lane bandwidth over today's PCIe 3.0 hardware.

Now, the organisation has confirmed that they plan to release their documentation for PCIe 5.0 version 1.0 this quarter (Q1 2019), months before PCIe 4.0 becomes available in mainstream desktop and datacenter processors. PCIe 5.0 will be backwards compatible with PCIe 4.0, 3.x, 2.x and 1.x.

This means that within two years PCI-SIG will have upgraded their PCI Express standard to offer 32GT/s of bandwidth within two years, which is fast enough to utilise the maximum potential of mainstream NVMe SSDs like the Samsung 970 Pro SSD over a single PCIe 5.0 lanes, which is an astounding achievement. 

It is worth noting that it will take some time before PCIe 5.0 becomes available on mainstream hardware. PCI-SIG released the PCIe 4.0 standard in October 2017, with AMD planning to launch their first PCIe 4.0 compliant processors in "mid-2019". Intel has not revealed their PCIe 4.0 plans on their public product roadmap. With this in mind, PCIe 5.0 shouldn't be expected on mainstream hardware platforms until 2021. 

Version 0.9 of the PCI Express 5.0 standard is already available to PCI-SIG members. 
   

PCI-SIG Releases Version 0.9 of their PCI Express 5.0 Standard  

You can join the discussion on PCI-SIG's plans to release their PCIe 5.0 specification this quarter on the OC3D Forums

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Most Recent Comments

17-01-2019, 16:22:33

NeverBackDown
It'll take even longer to come into development most likely as well. As the increase there frequencies the tracing from CPU to GPU becomes even shorter. It'll probably take a redesign of standard motherboard sizes if they want to get it closer.

Or way around that is just to keep the PCI4.0 trace length and just add more traces to effectively add more bandwidth, but that'll cost motherboard makers more money as they get more complex.Quote

17-01-2019, 20:16:26

tgrech
Controllers for earlier drafts of the spec already exist, its development was fairly uncoupled from 4.0's heavily delayed schedule, it could be a relatively quick rollout to enterprise, the gap between 3.0->4.0 being ratified was 7 years, 4.0->5.0 being ratified has only been two years, and the gap between hardware being available was technically even shorter.Quote
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