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Intel Details their Lakefield Processor Design and Foveros 3D Packaging Tech

Merging several products into a single, three-dimensional whole

Intel Details their Lakefield Processor Design and Foveros 3D Packaging Tech

Intel Details their Lakefield Processor Design and Foveros 3D Packaging Tech

Back at their architecture day in late 2018, Intel announced their Foveros 3D packaging technology, allowing silicon chips to be stacked on top of each other in a new and innovative way, creating a fully 3D processor. 

At CES 2019 Intel also revealed Lakefield, the company's first Foveros 3D processor, but now Intel has released a new video on their YouTube channel which better explains how their technology works, creating a great starting point for consumers who want to know more about the future of Intel's mobile products. Now, Intel has released a video on their YouTube channel that explains the technology behind Lakefield.  

For starters, Intel's Lakefield CPU is Intel's first "Hybrid Processor", offering a single 10nm Sunny Cove processing core alongside four smaller 10nm CPU cores. This combination enables Intel to deliver plenty of multi-threaded performance within a low power envelope while also providing their latest CPU IP for single-threaded scenarios, creating a low-power processor which offers incredible levels of versatility. 

Intel's Lakefield processor design is said to be 12mm by 12mm in size, which is an amazing feat given the package's inclusion of I/O on its bottom layer, CPU and graphics IP in the middle and DRAM on the top of the processor. Within this tiny package, Intel has fitted everything that a PC needs, which opens the door to a new range of ultra-mobile PCs. 

   At CES 2019, Intel previewed a new client platform, code named “Lakefield,” featuring the first iteration of its new innovative Foveros 3D packaging technology. This hybrid CPU architecture enables combining different pieces of IP that might have previously been discrete into a single product with a smaller motherboard footprint, which allows OEMs more flexibility for thin and light form factor design. Lakefield is expected to be in production this year.

While other companies have made pseudo-3D processor before, which are typically referred to as 2.5-D, Intel is the first to build a CPU that operates on several levels, rather than use a silicon interposer to connect several chips on a single level.

Unlike products like AMD's Vega series of graphics cards, the base layer of Intel's Foveros package isn't mostly dead silicon with a variety of interconnects, it is the I/O section of the processor, containing caches, PCIe connection points and other important circuitry. Beyond that, there is also a DRAM later that sits on top of Lakefield's compute chiplet, delivering insane levels of chip density.  

At this time it is unknown when Intel's competitors will be able to offer anything that utilises a fully 3D structure, though AMD has used 2.5-D chips for several generations, starting with their R9 Fury series of graphics cards and multi-chip processor designs since the release of EPYC and Ryzen Theadripper. 

Intel Details their Lakefield Processor Design and Foveros 3D Packaging Tech
  

Intel plans to produce Lakefield silicon this year for use in consumer products, delivering 10nm products in a unique 3D package. With Foveros Intel hopes to revolutionise the mobile PC market with a Hybrid CPU design, Generation 11 graphics, their latest Sunny Cove CPU architecture and their cutting-edge 10nm lithography. 

More information about Foveros is available here

You can join the discussion on Intel's Lakefield Processors and 3D Foveros packaging on the OC3D Forums

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Most Recent Comments

26-02-2019, 08:18:53

tgrech
I think a lot of companies have been looking into active die stacking for a while but the issue has always been that silicon is a thermal insulator & having stacks of heat producing insulation layers limits the possible power input to each of the layers to tiny levels if you want to sustain it to any degree. I guess they've either found a way to conduct heat better between the layers, or just reduced power use to levels where they have reasonable burst performance and not terrible sustained performance.Quote

26-02-2019, 08:41:19

WYP
Quote:
Originally Posted by tgrech View Post
I think a lot of companies have been looking into active die stacking for a while but the issue has always been that silicon is a thermal insulator & having stacks of heat producing insulation layers limits the possible power input to each of the layers to tiny levels if you want to sustain it to any degree. I guess they've either found a way to conduct heat better between the layers, or just reduced power use to levels where they have reasonable burst performance and not terrible sustained performance.
Yeah. In my eyes that is the reason why this is being used first on a mobile-focused product. Low TDPs and less chance of any thermal problems.Quote

26-02-2019, 14:23:51

meuvoy
Assuming thermals are dealt with, I can very easily see AMD responding to that by replacing the DRAM layer with a up to 32GB HBM layer on their design and retire DRAM for good... Just because they can...

What I don't like here is eventually both companies will end up eating DRAM sticks and placing them inside the CPU, and we'll be stuck with whatever amount of RAM we bought with our CPU. I don't know if this will be ultimately good or bad, I mean it's great performance-wise as RAM will be so close to the CPU but knowing intel, they will probably bundle cheaper CPU's with really low amounts of RAM so that we buy the really expensive CPUs to get RAM...Quote

26-02-2019, 17:09:54

WYP
Quote:
Originally Posted by meuvoy View Post
Assuming thermals are dealt with, I can very easily see AMD responding to that by replacing the DRAM layer with a up to 32GB HBM layer on their design and retire DRAM for good... Just because they can...

What I don't like here is eventually both companies will end up eating DRAM sticks and placing them inside the CPU, and we'll be stuck with whatever amount of RAM we bought with our CPU. I don't know if this will be ultimately good or bad, I mean it's great performance-wise as RAM will be so close to the CPU but knowing intel, they will probably bundle cheaper CPU's with really low amounts of RAM so that we buy the really expensive CPUs to get RAM...
servers will always require more RAM, so I'd imagine that on-die DRAM would act more like a large level 4 cache and have the option for external expansion.

Hmm, if Intel went down that route and had a large CPU L4 DRAM cache, using Optane instead of DDR? would make a lot more sense. Now there's an idea.Quote

26-02-2019, 18:23:53

tgrech
I think it'll be a long before before the benefits of stacked DRAM on an active die outweighs the thermal limitations enough to warrant putting it on high power chips, Foveros is a step in the direction but the actual interconnects are still quite traditional, so many of the benefits of say TSV stacked memory that you see with HBM don't apply here, it's just to keep the package compact atm.Quote
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