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AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans

A lot will change, especially with Genoa.

AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans

AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans

At the HPC AI Advisory Council's 2019 UK Conference, which took place on September 16/17th 2019, AMD's Martin Hilgeman revealed some early details about AMD's next-generation Zen 3 Milan architecture and the company's planned Zen 4/Genoa architecture. 

During his presentation, AMD's Martin Hilgeman, their Senior Manager of HPC applications, revealed slides which confirm that AMD's upcoming "Milan" series of Zen 3 processors will release on AMD's existing SP3 server socket, support DDR4 memory and offer the same TDP and core count ranges as the company's ROME series of processors. 

This slide appears to dispell the rumours that AMD planned to release Milan with a 4x SMT implementation, which alleged that Zen 3 would offer users four threads per CPU core. It looks like the main source of performance improvements from Zen 3 will come from IPC enhancements and clock speed gains, rather than increases in core/thread count. Hopefully, this means that Zen 3 will focus on single-threaded performance and core architecture improvements. 

Moving on to Zen 4/Genoa, Helgeman states that Zen 4 is still in its design stages, which means that server makers and other customers have the opportunity to influence Genoa's design. It is also confirmed that Zen 4/Genoa will release on a new SP5 socket, support a new memory type (likely DDR5) and offer users "new capabilities". 

  

AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans  

Zen 3

Over halfway through his presentation, AMD's Martin Hilgeman confirmed that Zen 3 would move away from Zen/Zen 2's split cache design, which split the L3 cache on AMD's CPU dies between two quad-core CCXs. This means that AMD could be moving away from its quad-core CCX design, creating an 8-core CCX design with Zen 3 or a CPU design that uses a different design scheme. 

Instead of offering two L3 caches that are 16MB in size (as seen in AMD's current Zen 2 design), AMD's Zen 3 core design will offer a combined "32+MB" of L3 cache between all eight CPU cores. This will lower potential inter-CCX latencies between the CPU cores in a single die and grant CPU cores better access to each chip's onboard L3 cache memory. 

The slide below also suggests that Zen 3's L3 cache will be bigger than what was seen in Zen 2. This means that Zen 3 could offer a larger, combine L3 cache, granting all CPU cores better cache access while also providing the potential for more cache capacity. This could lower some internal CPU latencies, and allow Zen 3 processors to cache more data on-die. These changes could be beneficial for Zen 3's gaming performance, given AMD's existing marketing for "GameCache", and its benefits for Zen 2. 


AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans  

Based on these slides, Zen 3 will mark another major design change for AMD's Zen CPU architecture, offering changes what will be hugely beneficial for the processor's internal cache latencies. While little is known about AMD's Zen 3 core design, these slides show us that AMD's next-generation architecture aims to mitigate more of the shortcomings of AMD's existing designs. These downsides were already largely reduced with Zen 2, but Zen 3 seeks to take things to another level. 

You can join the discussion on AMD's Zen 3 core design, and Zen 4/Genoa plans on the OC3D Forums

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Most Recent Comments

04-10-2019, 22:56:13

NeverBackDown
This was the natural progression and this is going to be a serious CPU. Working on 7nm+ as well should also help push IPC further.Quote

05-10-2019, 04:27:16

Dawelio
I assume this is quite far away, seeing as 3rd gen just recently launched?... And will it be compatible with AM4 or no?...Quote

05-10-2019, 05:04:48

g0ggles1994
Quote:
Originally Posted by Dawelio View Post
I assume this is quite far away, seeing as 3rd gen just recently launched?... And will it be compatible with AM4 or no?...
I'd hazard a guess that Zen 3 will be the last consumer CPU on AM4 as it fits the 'AM4 support until 2020' timeframe. Then Zen 4 will go onto AM5 with DDR5 and PCIe 5.0 after the Zen 4 based EPYC line is launchedQuote

05-10-2019, 17:37:46

WYP
Quote:
Originally Posted by NeverBackDown View Post
This was the natural progression and this is going to be a serious CPU. Working on 7nm+ as well should also help push IPC further.
Yeah. AMD needs to minimise the downsides of their Zen processor design, and eliminating inter-CCX latencies will be an important step. There will still be inter-die latencies, but giving each CPU core full access to 32+MB of L3 cache is a big deal.

A lot of the reason behind the old "each CCX has four cores" design was due to AMD's restricted budget. It allowed AMD to use quad-core CCX's in mobile and desktop parts without too much redesigning. AMD's original Zen CPUs needed to be cheap to develop over multiple product stacks. Remember that AMD didn't even make a profit back then.

7nm+ will help, but IPC comes from core design changes, not a node shrink. A new node can help with clocks, power and transistor size scaling. The IPC boosts come from core design changes. 7nm+ will be a minor leap from 7nm (when compared from the shift from 14/12nm to 7nm), so Zen 3 will rely on big design changes.

Quote:
Originally Posted by Dawelio View Post
I assume this is quite far away, seeing as 3rd gen just recently launched?... And will it be compatible with AM4 or no?...
Zen 3 is expected in summer 2020. AM4 compatibility is expected, as Zen 4 should be when AMD moves to DDR5.

Quote:
Originally Posted by g0ggles1994 View Post
I'd hazard a guess that Zen 3 will be the last consumer CPU on AM4 as it fits the 'AM4 support until 2020' timeframe. Then Zen 4 will go onto AM5 with DDR5 and PCIe 5.0 after the Zen 4 based EPYC line is launched
This is my guess as well. If Zen 3 Milan can use the same socket as today's EPYC parts, then there is no reason why Zen 3 Ryzen won't get the same treatment.

AMD's next socket will be a push to DDR5, something that actually requires a socket change. Yes, they could make CPUs that support both DDR4 and DDR5, but if we are honest that tactic has never really worked that well in the consumer market. Some Skylake motherboards supported DDR3 IIRC, but I don't think I have seen anyone on this forum using one of those boards.Quote

05-10-2019, 18:11:36

AlienALX
It was hugely important with Phenom 2 CPUs that supported DDR2 and 3. However things have changed since then and we love throwing things away these days.

I wonder when all of the planet savers are going to realise that e waste is beyond terrible. Course not, 'cause take my money and give me a new phone Quote
Reply
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