AMD details its 3D packaging technology at Hot Chips 33
The future is 3D and AMD is ready!
Published: 23rd August 2021 | Source: Computerbase.de |
AMD details its 3D packaging technology plans at Hot Chips 33
When it comes to chiplet packaging technologies, there is no one-size-fits-all approach to three-dimensional chip designs. A critical aspect of future processors will be how designers mix and match these technologies to create the most performant, power-efficient, and cost-effective solutions.
Discussing the technology, AMD's Raja Swaminathan called the design challenges of 3D packaging "PPAC", which stands for Power, Performance, Area, and Cost. In some cases, otherwise ideal packaging solutions may be too costly for mainstream products for cost reasons. Alternatively, the high cost of some technologies may be worthwhile due to performance and power-efficiency benefits.
In time, AMD plans to utilise more complex 3D packaging technologies to create future CPUs and GPUs. As these technologies are utilised, the design of future processors will be fundamentally changed. Before now, single-chip SOCs were commonplace, but over the next decade, single-chip solutions may become the exception, rather than the norm, for the high-end PC market.
AMD highlighted that their existing 3D packaging technology enables die-on-die stacking, allowing AMD to stack additional L3 cache on their Ryzen 5000 series processors. This allows AMD to add 64MB of L3 cache to their Ryzen 5000 series compute chiplets, tripling its available L3 cache. The hybrid bonding technique connecting this L3 cache to AMD's Zen 3 processors are 9-microns in pitch, which is denser than Intel's 10-micron Foveros Direct technology.
As 3D packaging technologies improve, CPU makers will be given new design options that will transform the industry. AMD is currently placing more cache on top of their CPU dies, but the future of this technology will enable DRAM on CPUs, cores on top of CPU cores, and even more complex solutions.
In time, some design elements of CPU cores will be placed on top of others. This circuit splitting will allow hotter elements of cores to be placed above cooler elements while dramatically decreasing the PCB footprint of processors. Such a solution will dramatically increase compute density while lowering the potential thermal downsides of 3D chip design.
3D packaging will fundamentally change the way that high-performance processors will be designed, and the correct utilisation of these technologies will dictate which semiconductor companies will be successful over the coming decade.
Let's be clear here. You will hear a lot more about 3D processor design and the benefits of modern packaging technologies over the coming years. AMD's innovative 3D V-Cache is only the start of AMD's planned 3D chiplet revolution, and you should expect other companies to invest in similar technologies.
Intel already has its Foveros and EMIB interconnect technologies, and we can expect them to invest further into 3D packaging technologies as they grow their foundry business and continue to create x86 processors and other high-end semiconductor products.
AMD's 3D Chiplet technology reportedly deliver a 3x increase in interconnect efficiency when compared to Micro Bump 3D and a 15x increase in interconnect density. These changes grant AMD higher levels of signal integrity and lower the power loss from their interconnects.
In time, we will learn more about the benefits and downsides of 3D packaging technologies. For now, AMD has made it clear that 3D packaging technologies will be a major driver within the semiconductor market moving forward, and that the possibilities offered by the technology are endless in scope.
You can join the discussion on AMD's 3D packaging plans on the OC3D Forums.
Most Recent Comments
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Originally Posted by NeverBackDown
My mind will be blown once we get actual CPU cores on top of other CPU cores. Just unbelievable and an amazing feat of engineering.
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