Super SSDs Not Too Far Off
Researchers in Japan are claiming a breakthrough in NAND Flash cell design that will allow the development of super SSDs with faster write speeds and a longer lifespan. The reported feat has been achieved by a joint research team from University of Tokyo Engineering Department and the Frontier Device Group within Japan’s Advanced Industrial Science and Technology Institute.
Led by Professor Ken Takeuchi and Shigeki Sakai, the team has designed a ferroelectric Flash memory cell, which they have dubbed Fe-NAND. The new cell features a non-volatile Page Buffer, which distinguishes it from traditional flash cells. Traditional cells are designed around an electrically isolated Floating Gate (FG) layer, with a Control Gate above it. The charge within the FG layer acts as the on-off switch and decides when the Control Gate will conduct or resist a current and thereby store the binary 1 or 0.
The insulated casing around the FG layer allows it to hold the charge indefinitely, even in the absence of a power supply. The capacitative connection between the FG and the rest of the cell allows free two-way movement of electrons through quantum tunnelling without the need for an electrical connection between the two parts.
The new cell designed by the Tokyo scientists is based on the same principle; however, the major difference is in the composition of the layer. Their cell uses a ferroelectric layer – SrBiTaO – instead of FG. This layer has the capacity to retain a small amount of information at all times as it can be permanently polarised.
Additionally, this polarisation requires a much lower voltage than the one required to charge the FG layer. In practical terms, this means that their cell requires just 6V of power compared to the 20V plus of electricity required by FG-based Flash cells.
In addition to being greener, the new cell also boasts of a much longer write-life than traditional ones, which run out of steam in about 100,000 write cycles. The ferroelectric Flash cell reportedly has the ability to continue working for 100 million write cycles, making it that much more reliable.
By adding a non-volatile Page Buffer to their cell, the Tokyo researchers have also created better data writing algorithms, which allow the cell to have higher write speeds. The new algorithms check the fragmentation of data across Flash cells to speed up random write operations. The Page Buffer ensures that there is no data loss even in the event of a power loss while the data is being buffered before being written out of the Flash.
With the possibility that the new chips can be fabricated in a 10nm process – a size not possible to employ for traditional Flash cells – Fe-NAND chips are also likely to be much more cost effective compared to the traditional cells.
The technology, which is still in laboratory phase, was presented in detail by the research team at the 2009 Symposium on VLSI Circuits in Kyoto this week. The researchers are hopeful that they will be able to transcribe the process from the laboratory into commercial production very soon.