Intel Core i7 Presentation
"OC3D were present at Intels recent Core i7 presentation at Heathrow. We'll take a look at some of the new features and what they do"
Integrated Memory Controller (IMC) & Quick Path Interconnect (QPI)
One of the massive changes that comes with Nehalem is the 'on chip' DDR3 integrated memory controller which is located in the "uncore". While AMD has been using an IMC for some time, Intel have taken it one step further with their triple-channel memory controller which offers massively increased bandwidth.
When the first Nehalem CPU's are released, they will feature the triple-channel DDR3 memory controller which means that in order to gain maximum bandwidth from the platform, you will need to run three DDR3 memory modules. Intel confirmed that upon release, there will be triple-channel available from leading memory vendors.
The Nehalem IMC is pretty scalable too: besides offering massively high bandwidth and extremely low latencies, the number of memory channels can be varied - both buffered and non-buffered memories are supported and memory speeds can be adjusted all based on the market segment that the processor will be aimed towards. We should expect lower end, less expensive dual-channel parts at some point in the future, but no time scale was provided.
Also, at launch, the IMC on Nehalem will only officially support PC3-8500 memory but we were told that is going to increase with time. This can of course be overclocked and we were shown some slides giving performance indicators, but sadly I'm not allowed to show them (sorry). Also worth a mention is that there will be NO DDR2 support at all.
Another necessary addition that Intel has been talking about for a while is the move away from the front side bus architecture and to their new Quick Path Interconnect (QPI). QPI was previously known as Common System Interface (CSI) and is Intel's answer to AMD's Hyper Transport.
The QPI on Nehalem is a direct connect architecture that is point to point and will transmit data from socket to socket as well as from the CPU to the chipset. The QPI will scale according to the segment each CPU is targeted at and also on the number on CPU's per platform. As the number of CPU's goes up as does the QPI's as shown in the bottom picture in the slide to the left.
One of the reasons it was necessary to move to the QPI was because of the above mentioned IMC. The QPI is also a requirement for efficient chip-to-chip communications where one CPU needs to access data that is stored in memory on another
CPU's memory controller.
Each QPI link is bi-directional supporting 6.4 GT/s (Giga Transfers) per link. Each link is 2-bytes wide so you get 12.8GB/s of bandwidth per link in each direction which equates to a total of 25.6GB/s of bandwidth on a single QPI link.
The top of the line Nehalem processors (i.e. Extreme) will have two QPI links while mainstream versions will only have one.
Up until now most of what I have written about isn't exactly new information and most of it has been floating around for a little while, however something that only came to light within the last month or so was the implementation of the power consumption and regulation logic in the processor.
What Intel revealed was that rather than using simple algorithms for switching off the power planes of the new Nehalem cores as in previous CPUs, the Core i7 will feature a complete on-die microcontroller called the Power Control Unit (PCU). This chip consists of more than a million transistors which, in comparison is somewhere in the ball park of the transistor count on the Intel 486 microprocessor!
This new controller, which has its own embedded firmware, is responsible for managing the power states of each core on a CPU and takes readings of temperature, current, power and operating system requests.
Each Nehalem core has its own Phase Locked loop (PLL) which basically means each core can be clocked independently, similarly to AMD’s fairly new Phenom line of processor. Also similar to Phenom is the fact that each core runs off the same core voltage. But this is where I'll stop comparing Nehalem to Phenom as the difference is that Intel have implemented their integrated power gates.
When creating the power gate, Intel's architects had to work very closely with their manufacturing engineers to create a material that would be suitable to act as a barrier between any core and its source of voltage as seen in the slide below. At the time I couldn't really see what the slide was showing, and even now I struggle. However, it's relevant so it should be here.
What the power gate brings to the table is that while the CPU is still using a single power plane/core voltage, it can totally shut off (or very very close) any individual core by stopping the voltage getting to it during deep sleep states. This differs from the current situation in which all cores have to run at the same voltage and this applies for Intel and AMD CPU's. At present if one or more cores are active in a CPU then the other cores can't have their voltage lowered, which means the idle cores will still be leaking power while not in use.
In a little more detail, the power gates allow any number of cores on a CPU to be working at normal voltages, while any cores idling can have their power shut off completely which in turn reduces idle core power leakage dramatically. It was asked why this hasn't been seen on previous processors and Ronak said that there has never been a suitable and reliable material to use as a gate until now.
This is just the basics of what the CPU offers. There is a lot more to the CPU and power gates than I can explain in this article, and to fully explain it would take up several more pages and probably bore you half to death. So moving on.....
On to Turbo Mode and final thoughts
Most Recent Comments